John

OBJECTIVE

I am looking for challenging project in emerging technologies in VLSI domain with excellent satisfaction, both professionally and personally.

SKILLS

• Languages      
  Verilog, C
• EDA Tools Knowledge 
  ModelSim,VCS
  Xilinx 9.1 I ISE
  Altera Quartus II  
  Leonardo Spectrum 
  Iverilog
• Operating Systems         
  Windows
• Domain Knowledge        
  Image Processing
• HDL Design Entry       
  Emacs
• Technical Skills
  RTL Design and FPGA Synthesis
  Test Bench Development 
  FPGA Design Flow
  Digital Design
  Synthesize using Xilinx ISE
  Synthesize using Quartus II tool 4.0   
  State Machine Design

EXPERIENCE

1.Reach Technologies and Consulting Pvt Ltd., Bangalore

   Hardware Engg.(Nov 2005 till now)
   Primary responsibilities include RTL designing and functional Verification through simulation.

PROJECT EXPERIENCE

1) FPGA Porting of DWT Module

• Project Description
  DWT RTL is complete and has evaluated on FPGA. The objective is to test the RTL on an FPGA it  using Synthesizable Test bench.

    Environment             Quartus II 5.1(Megafunction), Simulation modelsim 5.
    Functionality             FPGA Porting of DWT Module
    Duration                    Feb 2007 to December 2007
    Role                          Design RTL code and created test plan.
   Team Size                 4

Responsibility

• Developed  Synthesizable Test Bench.
• RTL coding to apply the stimuli and compare the results.
• Integration of DWT RTL with the newly developed RTL.
• Signaling PASS/FAIL of DWT functionality through a GIO port.
• Obtain images of different size ( up to 128x128 ) for experimental purposes.

2) Image sensor data reader Module

• Project Description
  The main objective of this image sensor data reader is handles timing generation and data transfer from image sensor.

     Environment                 Synthesis xilinx, Simulation modelsim 5.5
     Functionality                 Timing generation and data transfer from image sensor.
     Duration                       Aug 2006 to December 2006
     Role                              Design RTL code and created test plan.
     Team Size                    2

Responsibility

• Implementing in Synthesizable RTL code.
• Creating test bench to verify function of image sensor data reader.
• State Machine Coding.

3.)Universal Asynchronous Receiver and Transmitter

Environment             Synthesis xilinx, Simulation modelsim 5.5
Functionality             Create Bus function module [BFM]
Duration                    March 2006 to June 2006
Role                          UART- BFM Developer
Team Size                2

• Project Profile

 This was part of the mobile phone module. The objective of the project was to integrate the UART core for a serial communication pixel.

Responsibility

• According to the Specification, Created Test plan for UART Transmitter.
• Functional Verification of the UART Core, Created BFM for UART Transmitter.
• Generated Test cases, to verify the function of the UART Transmitter.
• Test & Debugged the UART Core.

4)Image Scaling

• Project Description

Image Resizing Core provides facility to shrink or enlarge images according to user requirement. It supports Picture in Picture (PIP) facility in Television sets. It can be used with grayscale, true color, or binary images. It follows the Analogue TV Standard followed in India, Japan, etc. are PAL, whose Resolution is 720×576.

Environment             Synthesis xilinx, Simulation modelsim 5.5
Functionality             Development of image scaling IP
Duration                   Jan 2008 to till date
Role                          Implementing RTL code.
Team Size                6

Responsibility

• Designing of the nearest neighbor algorithm.
• Implementing in Synthesizable RTL code.
• State Machine Coding

Protocol’s knowledge        

• AMBA-AHB protocol.
• AMBA-APB protocol.
• UART
• I2C Bus Protocol

QUALIFICATION

Bachelor of Engineering in Electrical and Electronics(2000 – 2004 )
 Madurai kamaraj University
 Madurai
 Marks scored 70%

PERSONAL DETAILS

Fathers Name          Mr. D.Mahalingam
Date of Birth            15/11/1981
Sex                          Male
Marital Status           Single
Present Address     32,2nd Floor,Vikas bhawan,Bangalore

I hereby declare that the above information furnished by me is true to the best of my knowledge and belief.

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